HyperTransport speeds up

STILL REMEMBER HyperTransport? Well, the fast chip-to-chip interconnect, now in its seventh year of existence, has not given up just because a bad day - let's make it a year - at the AMD processor races.

Companies including Broadcom, Altera, Nvidia and such are actively pushing HT in a variety of apps not exactly related to the AMD CPUs, like ultrafast networking, FPGAs and non-X86 CPUs. And, it is matching its new competitor, Intel QuickPath, in the speed department right now.

In about eight hours, Mario Cavalli, GM of HyperTransport consortium, is to announce the HyperTransport 3.1 spec, which adds the 2.8, 3.0 and 3.2 GHz clock speed settings to bring the 2 x 16 bit bidirectional standard implementation bandwidth towards 6.4 gigatransfers per second, or 51.2 Gigabytes/s for us ordinary mortals.

The HTX3 matching spec for the slot and board products accessing the HT-enabled CPUs directly was also updated to the full HT3 speeds (5.2 gigaxfers/s right now) plus link splitting on a single connector to allow two HT CPUs - or, why not, GPUs - to access a single cards simultaneously. Now this would allow some interesting successor designs for the CrossFire and SLI, with larger GPU arrays connected on HTX slots.

Importantly, with the updated HTX slot and board spec, HyperTransport has fully defined ultrafast chip-to-chip, board-to-board AND box-to-box links. QPI still lacks on the last two, which in my mind is a miss - as Intel's initial workstation & HPC server Nehalems are only DP Gainestowns, a defined " External QPI" spec at this point would help offer a competitive solution to AMD four and eight socket MP servers, getting more popular as the "fat node" concept is coming back with a vengeance.

Talking about coming back with a vengeance, AMD CPU group is still far from that - but some good vibes are spread around: besides somewhat improved recent 65 nm quad core OC results above the 3.3 GHz mark, the rumour is that the 45 nm 6 MB L3 parts, if you're lucky, might give you 4 GHz in OC mode. Would that translate into faster default speed bins? I surely would like to see a 3.2 GHz Shanghai part, at least would compete very well against Nehalems in the HPC area. µ